Recent developments in memory technology may have resulted in the emergence of more advanced memory structures to supplement and/or replace traditional dynamic random access memory (DRAM). Accordingly, a given memory architecture in a computing system might include many different memory pools, with each pool having a different access latency, bandwidth and/or other properties. Multiple computing cores may access the various memory pools through a shared buffer that has a finite number of entries. Due to the non-uniform memory access (NUMA) latencies of the memory pools, requests to access higher latency pools may dominate the shared buffer over time. For example, if Pool A is relatively “fast” and has lower access latencies (e.g., 50 ns) and Pool B is relatively “slow” and has higher access latencies (e.g., 500 ns), requests to access Pool A might be serviced ten times faster than requests to access Pool B, on average. As the Pool A access requests are quickly serviced and removed from the shared buffer, they may be replaced with slower requests for Pool B. In such a case, the shared buffer may ultimately fill up with requests to access Pool B. Accordingly, the process(es) generating the Pool A requests may experience a negative impact on quality of service (QoS) and/or performance.